The present invention relates to synchronizing a sampling signal to a clock signal.
Integrated Circuits (IC) need to be tested to assure proper operation. During test, the IC, as a device under test (DUT), is exposed to stimulus data signals of an Automatic Test Equipment (ATE). The IC transmits corresponding response data back to the ATE. The ATE measures, processes and usually compares this response data with expected responses. The ATE usually performs these tasks according to a device-specific test program.
ATE's with decentralized resources based on a per-pin architecture are known, wherein during test, each pin of a multiple of pins of the DUT is connected to one ATE pin electronic. These ATE's further comprise central resources, in particular for controlling the sequence and timing of applied test stimulus vectors. The per-pin architecture generally enables high performance and scalability. Examples for ATE with per-pin architecture are the Agilent 83000 and 93000 families of Semiconductor Test Systems of Agilent Technologies. Details of those families are also disclosed e.g. in EP-A-859318, EP-A-864977, EP-A-886214, EP-A-882991, U.S. Pat. No. 5,499,248 and U.S. Pat. Nos. 5,453,995.
A digital data signal comprises a stream of discrete values or data. In the case of binary data, the signal represents a certain sequence of two values, e.g. of the values “0” and “1”, wherein the values are represented each by a pulse having a certain format e.g. having a return-to-zero (RZ) format or a non-return-to-zero (NRZ) format, and a certain length. (As simple example for an NRZ format, the signal takes a first constant value for a “0” and a second constant value for a “1”. For recovering the data of the digital signal at a receiver, it is necessary to know the timing of the digital signal, i.e. to know the length of each pulse (=clock frequency) and the beginning of each pulse (=clock phase) to be able to correctly sample the received data stream. Thus, clock information has to be exchanged between data sender and receiver.
Traditionally, the data signal sender transmits additionally a clock signal having a frequency corresponding to the bit rate of the transmitted data and a phase corresponding to the timing of the bit edges. This clock is used at receiver's side either directly to sample the received signal or to adjust a receiver's clock for sampling the received signal. In the latter case, the frequency of the clock signal may have a fraction or a multiple of the bit rate.
A problem of synchronization is that the data and clock signals are affected by disturbances that might lead to phase drift or phase jitter. Due to the high data speed in modern test systems, small deviations of the receiving clock with respect to the sending clock might already lead to an erroneous recovery of the received signal.